Neat project - there are already a couple of good open FPGA projects. Have a look at Dirk Koch's and the FABolous teams work. They are doing exceptional work.
But all open FPGA projects miss the IO required for a good design. They do not have any serdes hardware nor DDR IO cells.
This project seems to have a serdes block which seems to wrap whatever is in the PDK. Didn't look too far down but from a cursory glance it looked like it was built for an internal clock of 50 MHz (clock default to 20 ns) with an oversampling of 8: 400 MHz
If those numbers are at all right it puts it in useful territory. Very much so for a first spin
For a first spin it looks overall pretty useful. The only nitpick I have would be that `operation` on the DSP tile should be from fabric instead of config (hardcoded in bitstream) otherwise I don't see a convenient way of resetting the accumulator(?)
Thanks for the suggestion on the DSP. Maybe I'll add new DSP tiles that are reconfigurable and keep the config based DSP tiles. I designed Aegis's Terra 1 to be a "good enough first gen" so that's why things are the way they are. I didn't want to over commit on the design for a first generation.
Yeah, I did see there's been attempts but none really satisfied what I wanted out of it. I do know of FABulous and it seems good but not quite what I wanted. You can see that aside from yosys and nextpnr, it is quite self contained and even provides a very easy way of defining new silicon with Nix.
I know that IO is really the 2nd thing which sells FPGA's. I did design a basic serdes hardware that should just work for this first generation. I do want to do DDR IO cells in the future.
You can come work with us/for us and scale your SerDes design for us. That gets you actual wafer mask sets taped-out, a million chips and a WSI, not just test chips. A succesful SerDes will get you a job (at least in Europe).
How fast will the SerDes run, 50 Mhz? It is not clear to me from the serdes_tile.dart source code.
Can you share the verilog files?
Nice specs! Looking forward to seeing how this and the other projects on Waferspace goes. Being able to produce 1k chips at a reasonable price will hopefully do wonders for open hardware / open silicon.
Yep, Aegis's Terra 1 is designed to be "good enough" for the first generation. I do plan on expanding the Terra family of FPGA's if there's enough interest. I do want to work my way up to 100k LUT's.
What are your thoughts on including a RISC-V hardcore along with the gates? Because for almost all projects I can imagine using FPGA for, I would want a microcontroller also. This might however be slightly colored by me being a software/firmware first type of electronics engineer. Thinking especially for the smaller gate counts, like under 10k - because there a soft CPU takes up very precious resources.
1k chips for $4000 or $7000 at 180nm is (a lot) more expensive than 180nm at MOSIS or Europractice, I wound not call it reasonable, especially because the EDA software tools and PDK used are inferior.
As someone who has only dabbled with FPGAs before, this is incredible to see all the steps end-to-end for silicon development! I feel like the articles I've read always leave out details in one part or another, so it's interesting to see all the nix dependencies and build steps.
This is quite a milestone for open silicon. Having a completely auditable path from RTL down to GDS targeting the GF180MCU via wafer.space is no small feat-especially pulling it all together with a Nix-integrated toolchain and Dart for the hardware generation.
On the I/O side, getting even a basic 400MHz oversampled SerDes into a first-gen test chip puts this way ahead of most academic open FPGA efforts.
Really looking forward to seeing the Terra family expand and how the test chips perform.
Is there a way in the DSP (that's the only one I looked at) to instead of going through a mux at the end just put the output flop optionally in a transparent mode if registering isn't enabled? I don't know if that's possible with the tooling but it seems like it'd save resources and reduce fanout.
The problem is you can make test chips like Aegis for around $10 (depending on the yield, on how many of the first 1000 chips actually work) but they are just that, test chips.
In the case of Morphle Logic we make wafer scale integrations (WSI) with 10 billion transistors at 180nm for $750. That yields around 300 million 'gates', the largest commercial FPGA's barely get to 3 million. So our Morphle Logic WSI is the largest and fastest (up to 12 Ghz) FPGA you could get if we can find a few hundred buyers who want to pay up front (crowdfunding). Please email me if you are interested in such a enormous fast FPGA.
I'll buy an Aegis FPGFA test chip just to find out how hard it is to test a test chip.
Good luck RossComputerGuy, I hope you get working chips back. The same fab and supplier lost our first taped-out chips in the mail... and then they went bankrupt.
[2] "If an elderly but distinguished scientist says that something is possible, he is almost certainly right; but if he says that it is impossible, he is very probably wrong." - Arthur C. Clarke
I guess the AMD Versal Premium VP1902 adaptive SoC has 18.5 million cells. The VU19P is more than half in LUT count.
Morphle Logic WSI has over 47,169,811 yellow cells. You could say that a single yellow Morphle Logic cell is more complex than ten Versal cells, but it's an apples and oranges comparison. However you count it, the $500 Morphle Logic WSI (cost price) has 10 billion transistors, the AMD Versal Premium cost over $100.000 and is effectively smaller in terms of gates, LUTs or cells even though it has 138 billion transistors.
If I made the Morphle Logic WSI in 2nm TSMC, it would have more than 52 trillion transistors [1], at least 245,283,018,867 yellow cells and cost over $22.500. You could easily emulate several AMD Versal Premium VP1902 FPGA's on the wafer.
Tbh I did forget about versal but yes the PL of the VP1902 absolutely has more than 3 million logic gates no matter how you slice it. I have no doubt that there are non-fpgas with more, but it is a bit disingenuos to say they're orders of magnitude under where they actually are.
I'll also note that it has a ton of SRAM onboard which doesn't shrink well, so I'm not convinced just by that extrapolation that you could eclipse it with a simple lithography shrink. Unless you really meant several per wafer, which doesn't really feel like a hard target...
I struggled a bit to understand the explanation on github, but eventually got to something that made sense. It would have helped me if it said up front that
- 0, 1, N and Y pass the input signal on (works like a | or - in the input direction), and that
- when a circuit has both a 0 and 1 output value, the output becomes 0 (which is why 11 is an AND and not a OR)
Hopefully that's correctly understood? If so, maybe consider updating the explanation for the next person.
Also, a question: Does a 0 and 1 on the same circuit consume more power than two 0s or two 1s due to the conflicting values? Or is it solved with transistors at the cost of propagation delay? Or something else?
Thank you for pointing out I need to improve the explanations.
We made seven different implementations of Morphle Logic, some of which are lower power, use less transistors, different ways to do asynchronous logic or are based on superconducting josephson junctions instead of transistors.
In this particular case the two tokens probably consume the same amount of power regardless of their value, but only measurements will tell.
Neat project - there are already a couple of good open FPGA projects. Have a look at Dirk Koch's and the FABolous teams work. They are doing exceptional work.
But all open FPGA projects miss the IO required for a good design. They do not have any serdes hardware nor DDR IO cells.
This project seems to have a serdes block which seems to wrap whatever is in the PDK. Didn't look too far down but from a cursory glance it looked like it was built for an internal clock of 50 MHz (clock default to 20 ns) with an oversampling of 8: 400 MHz
If those numbers are at all right it puts it in useful territory. Very much so for a first spin
For a first spin it looks overall pretty useful. The only nitpick I have would be that `operation` on the DSP tile should be from fabric instead of config (hardcoded in bitstream) otherwise I don't see a convenient way of resetting the accumulator(?)
Thanks for the suggestion on the DSP. Maybe I'll add new DSP tiles that are reconfigurable and keep the config based DSP tiles. I designed Aegis's Terra 1 to be a "good enough first gen" so that's why things are the way they are. I didn't want to over commit on the design for a first generation.
Yeah, I did see there's been attempts but none really satisfied what I wanted out of it. I do know of FABulous and it seems good but not quite what I wanted. You can see that aside from yosys and nextpnr, it is quite self contained and even provides a very easy way of defining new silicon with Nix.
I know that IO is really the 2nd thing which sells FPGA's. I did design a basic serdes hardware that should just work for this first generation. I do want to do DDR IO cells in the future.
You can come work with us/for us and scale your SerDes design for us. That gets you actual wafer mask sets taped-out, a million chips and a WSI, not just test chips. A succesful SerDes will get you a job (at least in Europe).
How fast will the SerDes run, 50 Mhz? It is not clear to me from the serdes_tile.dart source code. Can you share the verilog files?
Nice specs! Looking forward to seeing how this and the other projects on Waferspace goes. Being able to produce 1k chips at a reasonable price will hopefully do wonders for open hardware / open silicon.
Yep, Aegis's Terra 1 is designed to be "good enough" for the first generation. I do plan on expanding the Terra family of FPGA's if there's enough interest. I do want to work my way up to 100k LUT's.
What are your thoughts on including a RISC-V hardcore along with the gates? Because for almost all projects I can imagine using FPGA for, I would want a microcontroller also. This might however be slightly colored by me being a software/firmware first type of electronics engineer. Thinking especially for the smaller gate counts, like under 10k - because there a soft CPU takes up very precious resources.
I've definitely had a thought about doing a hard core RISC-V SoC on a dev board.
1k chips for $4000 or $7000 at 180nm is (a lot) more expensive than 180nm at MOSIS or Europractice, I wound not call it reasonable, especially because the EDA software tools and PDK used are inferior.
As someone who has only dabbled with FPGAs before, this is incredible to see all the steps end-to-end for silicon development! I feel like the articles I've read always leave out details in one part or another, so it's interesting to see all the nix dependencies and build steps.
This is quite a milestone for open silicon. Having a completely auditable path from RTL down to GDS targeting the GF180MCU via wafer.space is no small feat-especially pulling it all together with a Nix-integrated toolchain and Dart for the hardware generation.
On the I/O side, getting even a basic 400MHz oversampled SerDes into a first-gen test chip puts this way ahead of most academic open FPGA efforts.
Really looking forward to seeing the Terra family expand and how the test chips perform.
There's also an open source Authenticator software with the same name.
Is there a way in the DSP (that's the only one I looked at) to instead of going through a mux at the end just put the output flop optionally in a transparent mode if registering isn't enabled? I don't know if that's possible with the tooling but it seems like it'd save resources and reduce fanout.
We make an asynchronous sea of gates runtime reconfigurable gate array chip very different from FPGA's but with the same use cases https://github.com/fiberhood/MorphleLogic/blob/main/README_M...
The problem is you can make test chips like Aegis for around $10 (depending on the yield, on how many of the first 1000 chips actually work) but they are just that, test chips.
In the case of Morphle Logic we make wafer scale integrations (WSI) with 10 billion transistors at 180nm for $750. That yields around 300 million 'gates', the largest commercial FPGA's barely get to 3 million. So our Morphle Logic WSI is the largest and fastest (up to 12 Ghz) FPGA you could get if we can find a few hundred buyers who want to pay up front (crowdfunding). Please email me if you are interested in such a enormous fast FPGA.
I'll buy an Aegis FPGFA test chip just to find out how hard it is to test a test chip.
Good luck RossComputerGuy, I hope you get working chips back. The same fab and supplier lost our first taped-out chips in the mail... and then they went bankrupt.
12 GHz on 180nm? Sorry, that's not possible. What's the actual clock speed?
Morphle Logic is asynchronous logic so there is no clock.
At 110nm I measured when a transistor was switching the second transistor on its output. I can prove it, can you disprove it?
A consistent 12Ghz signal cascade was (repeatedly) tested and confirmed on a 28nm asynchronous chip [1].
Why would it be impossible? [2].
We measure 800 Ghz and teraherz clocks on niobium superconducting Josephson Junctions [3,4,5].
[1] https://byrdsight.com/asynchronous-technology-has-its-time-f... ( See also on the slides in the video talk)
[2] "If an elderly but distinguished scientist says that something is possible, he is almost certainly right; but if he says that it is impossible, he is very probably wrong." - Arthur C. Clarke
[3] Ivan Sutherland Keynote Single Flux Quantum SFQ Ditigal Electronics Digital circuits totally distinct from Quan https://www.youtube.com/watch?v=KMVV3ErGSVY
[4] https://www.researchgate.net/profile/Jerome-Pety/publication...
[5] https://scholar.google.com/scholar?hl=en&as_sdt=0,5&qsp=3&q=...
You must be fun at parties...
VU19P = 3M gates how? It has more than 3M LUTs and each LUT is certainly > 1 gate
I guess the AMD Versal Premium VP1902 adaptive SoC has 18.5 million cells. The VU19P is more than half in LUT count.
Morphle Logic WSI has over 47,169,811 yellow cells. You could say that a single yellow Morphle Logic cell is more complex than ten Versal cells, but it's an apples and oranges comparison. However you count it, the $500 Morphle Logic WSI (cost price) has 10 billion transistors, the AMD Versal Premium cost over $100.000 and is effectively smaller in terms of gates, LUTs or cells even though it has 138 billion transistors.
If I made the Morphle Logic WSI in 2nm TSMC, it would have more than 52 trillion transistors [1], at least 245,283,018,867 yellow cells and cost over $22.500. You could easily emulate several AMD Versal Premium VP1902 FPGA's on the wafer.
[1] https://www.youtube.com/watch?v=vbqKClBwFwI
Tbh I did forget about versal but yes the PL of the VP1902 absolutely has more than 3 million logic gates no matter how you slice it. I have no doubt that there are non-fpgas with more, but it is a bit disingenuos to say they're orders of magnitude under where they actually are.
I'll also note that it has a ton of SRAM onboard which doesn't shrink well, so I'm not convinced just by that extrapolation that you could eclipse it with a simple lithography shrink. Unless you really meant several per wafer, which doesn't really feel like a hard target...
Interesting to see an alternative approach.
I struggled a bit to understand the explanation on github, but eventually got to something that made sense. It would have helped me if it said up front that
- 0, 1, N and Y pass the input signal on (works like a | or - in the input direction), and that - when a circuit has both a 0 and 1 output value, the output becomes 0 (which is why 11 is an AND and not a OR)
Hopefully that's correctly understood? If so, maybe consider updating the explanation for the next person.
Also, a question: Does a 0 and 1 on the same circuit consume more power than two 0s or two 1s due to the conflicting values? Or is it solved with transistors at the cost of propagation delay? Or something else?
Thank you for pointing out I need to improve the explanations.
We made seven different implementations of Morphle Logic, some of which are lower power, use less transistors, different ways to do asynchronous logic or are based on superconducting josephson junctions instead of transistors.
In this particular case the two tokens probably consume the same amount of power regardless of their value, but only measurements will tell.
Excellent. Put me down for a couple.
me too please