> The fix is to set bit 13 of MCSR24 to 1. MCSR24 is an internal CSR whose function is not described in the manual. After setting this bit, the lost update no longer occurs. Testing showed the performance loss is very small: single-core performance is unaffected, and multi-core performance drops only slightly.
> The fix is to set bit 13 of MCSR24 to 1. MCSR24 is an internal CSR whose function is not described in the manual. After setting this bit, the lost update no longer occurs. Testing showed the performance loss is very small: single-core performance is unaffected, and multi-core performance drops only slightly.
Presumably this is a so-called “chicken bit”.
Pretty much the definition of.
Some optimization that turned out to be buggy had a disable bit in an undocumented register.
> Presumably this is a so-called “chicken bit”.
For those who are out of the loop:
> https://lwn.net/Articles/744840/
See also
> https://en.wiktionary.org/wiki/chicken_bit
(click on "quotations") for a list of scientific texts in which this term occurs.
more like out of the coop
Famously, the first GPS satellites had one of these, in case Einstein was wrong...
https://www.quora.com/Why-did-the-GPS-system-initially-resis...
He wasn't.
Why does the western world care about Chinese CPUs, let them play in their sandbox with their own systems
Wang Miao? Is this the fault of sophons?