GPT-Synopsys brings together OpenAI frontier models with Synopsys' EDA technology and domain expertise, enabling the specialized model [to] directly operate Synopsys' tools. Engineers will delegate design objectives … with agents running tools, interpreting results, implementing changes, and iterating toward verified outcomes for engineer review.
“Agents will do all the engineering work. Engineers will delegate and review.” Lol, no, what the engineers are gonna do is get laid off.
Chips design is expensive. Partly because of engineering costs, partly because of manufacturing costs.
If costs go down enough,because of LLM's and possible manufacturing innovations, more chips will be designed, so maybe this will partially offset job loses.
> more chips will be designed, so maybe this will partially offset job loses.
This is HN mentality. But it is not how it always works. The first thought isn't we can make more money tomorrow by building more faster. It is we can make more money today by laying off all the people that we don't need now. Short-termism is the rule.
I think that’s more the norm in stability, where the economy when not a lot is happening/changing/improving, and so the economy is focused on efficiency as a method of competition. We are squarely not in efficiency mode right now, we’re in explore as fast as possible mode, as a lot of old underlying assumptions have changed, and there’s a huge amount of work to be done in reworking everything for the new assumptions. That means lots of opportunities, lots of money flying around, and bean counters getting outcompeted by people who’re focused on doing new things. Being too conservative does not serve you well in this regime. My two cents, anyway, I don’t think overall massive job losses are on the menu anytime soon, but massive job displacement/swapping, very likely.
For each Design Engineer, there are 3 Design Validation Engineers because going to fabrication is very expensive and it is unlike software where you can just do a git push and wait for the CI/CD pipeline to deploy code within minutes at no additional costs.
Eventually... But it is materially relevant if that happens in 2 years or 10.
While I think SWEs(yeah, not HW/chip but that's not my field) are cooked in 5 years, I think we'll be quite busy in the meantime fixing all the bugs that AI finds.
From an investment perspective, I think fabs like TSMC, Intel, and Samsung will benefit from better AI chip design tools.
If AI made it 100x faster and cheaper to build software, you suddenly have an explosion of software that need to be hosted. So companies like AWS/iOS App Store/cloud companies benefit.
If AI makes designing chips 100x faster and cheaper, you will have an explosion of custom chips for all sorts of applications. These chips still need to be physically made at TSMC, Intel, or Samsung.
Apple says it takes 3-4 years to design each Apple Silicon generation.[0] So the M6 was being designed in 2022-2023 already. Reports are that it costs hundreds of millions to a billion to design a cutting edge chip from scratch to finish.[0]
The cool thing is that we'll have niche ASIC chips for accelerating special applications that previously didn't have big of a market for someone to make a profit on. This is the same thing with software today. It's much easier to build custom software for a small niche and be profitable today than in 2022.
And given that Moore's Law is essentially dead in terms of density scaling, having an AI to automatically optimize the hell out of design and squeeze as much performance as possible out of the transistors could help us have a few more years of nice performance increase.
We just buried an ASIC design that was nearly finished.
Reason: There was a deviation that would've needed a mask change, but because of AI chip demand, the manufacturer wanted so much money for it, that we said screw it.
So we now have AI powered chip design tools that make chip design cheaper, but because of AI, chip manufacturing has become so expensive, that we can't afford it anymore.
> Manufacturers choosing not to scale with demand or not being able to scale with demand
In a vacuum, that would make sense.
But looking at how the industry works, the number of defunct companies, and how the whole industry got concentrated on the conservative companies, you start to understand that the reason they still exist is mainly because they don't ride fad waves.
It's not like chip manufacturing is a spot instance on AWS that you spin up and down when needed; these are multi-year, multi-billion dollar investments that require long-term demand studies. The AI approach of requesting a whole fab of demand for the next 5 years with a letter from Jason Hwang that says "trust it, bro" does not bring as much confidence as it appears.
> I see you are using Cadence IP in your project, unfortunately this is not allowed per the terms and conditions and you will be reported to the authorities
Also : create proprietary locked down eda->no data to train models->models suck at it->reach out to ai lab to rl on it -> expect users to pay for eda and the model.
... > I see you are using Cadence IP in your project, unfortunately this is not allowed per the terms and conditions and you will be reported to the authorities
EXACTLY, prepare to self deport immediately, push <proceed> to execute
Having written a lot of Tcl glue for PrimeTime and ICC, the hard part was never writing the constraints, it was knowing which timing violation to actually believe.
Toolcalls will end up disappearing to the other side and then you can download the end result - at a price - or arrange for manufacturing, but you'll have no idea about what is in the nice & shiny black box.
A question to those active in chip design industry: Are formal methods and formally proving a design more prevalent and normal in this industry compared to general software development?
Like for a Arm microcontroller design, do engineers thoroughly test and formally prove the correct functionality of every component? If that's the case, why silicon errata is a thing?
It’s called design verification, formal proofs happen mostly at the EDA tool level and largely already automated. Design verification focus on functional correctness of the chip for its intended use case
There are tools for formal verification of design input, and they are being used, but not for everything.
Why there are still errata for silicon
1. Writing a formal specification of your intended behavior is hard and the best verification tool doesn't help when your assertions don't encode the required or intended behavior. So even with 100% formal coverage, you would still get erratas. And some people don't write any formal verification, instead working with a simulation based approach (either hand-written test cases or random stimulus simulation)
2. Computation complexity of formal verification is exponential. At some point you simply can't formally prove the behavior of a design, because it just won't run on your server.
3. There's different levels of formal verification, not all of them are in the spec -> behavior path. For example, you could classify automated checks like logic equivalence between the synthesis netlist and RTL code as a formal verification. But that checks if the optimizer in the synthesis tool was correct, not that you wrote the correct RTL.
Compared to software formal methods have greater adoption. But there are a lot of things that fall under the “formal” umbrella.
The most common type that is used would probably be logical equivalence checking. Proving RTL and a netlist are equivalent is useful for catching synthesis bugs.
Or proving two netlists are equivalent after inserting test functions directly into a netlist, or some other netlist edit.
Property checking is what I use the most. You can check these during simulation which I wouldn’t call “formal” but you can also prove them using tools that use SAT solvers and whatnot to prove things mathematically.
As always, the tricky part of verification is writing the correct test or model. With formal we can use SystemVerilog assertions to write properties and sequences, but the difficulty in getting them right goes from trivial -> inscrutable very quickly.
It’s extreme easy to write assertions that pass and never realize your assertion was not doing what you thought and you weren’t proving what you meant to.
I haven’t used some of the more advanced tools so maybe they have ways to make this easier. But because of this I tend to just write assertions that are pretty easy to understand at a glance, and therefore closer to the trivial side of things.
If a peer has to solve a sudoku puzzle in their head to understand your work, then it’s unlikely the peer review will be worth anything. So I do what I can to make my work understandable at a glance (from a competent peer in the industry).
Of course making something simple can be quite challenging and often takes more time than leaving something complex and opaque.
I’ve never been involved in the foundry side of the work, and for ASICs, that is often half of the schedule.
Apparently SNPS share price gone up a little bit because of this. However, the rise didn't compensate their loss over the years. I keep wondering why EDA companies didn't get the hype like AI labs and Chip design companies.
I remember the stock taking a beating after Kimi K3 created all that buzz about the open model designing chips that could run itself (even though the chip in question seemed small in today's standard of massive AI chips). It was only a matter of time before Synopsys released an offering like this. I can almost see the meeting where the C suite demanded working with an external partner over anything in-house they could build.
Why the overall market cap is smaller than both Synopsys and Ansys combined before the merger still beats me tho.
Would be really nice honestly. But I don't think it will be coming anytime soon, it's just too expensive to build a chip.
The one-time costs for masks are just much more expensive as for PCBs, so wafer shuttle services are still really expensive when pooled PCBs are really cheap.
And any machines that would be cheaper for prototyping (direct laser writing or direct e-beam writing) don't scale to mass production.
You can already make (tiny) chips for a somewhat affordable cost with tiny tapeout.
But that's still not nearly as cheap as PCB prototypes and with much longer wait times.
“Agents will do all the engineering work. Engineers will delegate and review.” Lol, no, what the engineers are gonna do is get laid off.
Most of them anyway, and the cutoff bar will continue to rise.
Chips design is expensive. Partly because of engineering costs, partly because of manufacturing costs.
If costs go down enough,because of LLM's and possible manufacturing innovations, more chips will be designed, so maybe this will partially offset job loses.
The wish granting machine won't need the engineers for that. You'll just end up paying for the devices.
> more chips will be designed, so maybe this will partially offset job loses.
This is HN mentality. But it is not how it always works. The first thought isn't we can make more money tomorrow by building more faster. It is we can make more money today by laying off all the people that we don't need now. Short-termism is the rule.
I think that’s more the norm in stability, where the economy when not a lot is happening/changing/improving, and so the economy is focused on efficiency as a method of competition. We are squarely not in efficiency mode right now, we’re in explore as fast as possible mode, as a lot of old underlying assumptions have changed, and there’s a huge amount of work to be done in reworking everything for the new assumptions. That means lots of opportunities, lots of money flying around, and bean counters getting outcompeted by people who’re focused on doing new things. Being too conservative does not serve you well in this regime. My two cents, anyway, I don’t think overall massive job losses are on the menu anytime soon, but massive job displacement/swapping, very likely.
For each Design Engineer, there are 3 Design Validation Engineers because going to fabrication is very expensive and it is unlike software where you can just do a git push and wait for the CI/CD pipeline to deploy code within minutes at no additional costs.
So let's see.
Exactly. How 'bout “economize” chip design by reducing / eliminating human chip designers ... Go figure.
Eventually... But it is materially relevant if that happens in 2 years or 10.
While I think SWEs(yeah, not HW/chip but that's not my field) are cooked in 5 years, I think we'll be quite busy in the meantime fixing all the bugs that AI finds.
From an investment perspective, I think fabs like TSMC, Intel, and Samsung will benefit from better AI chip design tools.
If AI made it 100x faster and cheaper to build software, you suddenly have an explosion of software that need to be hosted. So companies like AWS/iOS App Store/cloud companies benefit.
If AI makes designing chips 100x faster and cheaper, you will have an explosion of custom chips for all sorts of applications. These chips still need to be physically made at TSMC, Intel, or Samsung.
Apple says it takes 3-4 years to design each Apple Silicon generation.[0] So the M6 was being designed in 2022-2023 already. Reports are that it costs hundreds of millions to a billion to design a cutting edge chip from scratch to finish.[0]
The cool thing is that we'll have niche ASIC chips for accelerating special applications that previously didn't have big of a market for someone to make a profit on. This is the same thing with software today. It's much easier to build custom software for a small niche and be profitable today than in 2022.
And given that Moore's Law is essentially dead in terms of density scaling, having an AI to automatically optimize the hell out of design and squeeze as much performance as possible out of the transistors could help us have a few more years of nice performance increase.
[0]https://fireflies.ai/blog/johny-srouji-and-john-ternus-inter...
[1]https://www.granitefirm.com/blog/us/2023/04/29/cost-of-chip-...
We just buried an ASIC design that was nearly finished. Reason: There was a deviation that would've needed a mask change, but because of AI chip demand, the manufacturer wanted so much money for it, that we said screw it.
So we now have AI powered chip design tools that make chip design cheaper, but because of AI, chip manufacturing has become so expensive, that we can't afford it anymore.
Nice.
AI didn’t make chip manufacturing more expensive
Manufacturers choosing not to scale with demand or not being able to scale with demand
Is what constrained the supply.
Hopefully will be fixed within a decade , then it’s cool new stuff all the way.
Why aren't boring, old process ASICs isolated from this mess?
When did chip demand skyrocket?
How long does it take to ramp up capacity?
> Manufacturers choosing not to scale with demand or not being able to scale with demand
In a vacuum, that would make sense.
But looking at how the industry works, the number of defunct companies, and how the whole industry got concentrated on the conservative companies, you start to understand that the reason they still exist is mainly because they don't ride fad waves.
It's not like chip manufacturing is a spot instance on AWS that you spin up and down when needed; these are multi-year, multi-billion dollar investments that require long-term demand studies. The AI approach of requesting a whole fab of demand for the next 5 years with a letter from Jason Hwang that says "trust it, bro" does not bring as much confidence as it appears.
Local manufacturing is the next open challenge in hardware. If a pizza can be baked locally, why not chips?
Pizza making smol machine, low precision, child baking big machine, trees expensive, can't have locally
Used to be a bakers oven was one per town, maybe big precise machine becomes cheap smol precise machine
> I see you are using Cadence IP in your project, unfortunately this is not allowed per the terms and conditions and you will be reported to the authorities
Also : create proprietary locked down eda->no data to train models->models suck at it->reach out to ai lab to rl on it -> expect users to pay for eda and the model.
... > I see you are using Cadence IP in your project, unfortunately this is not allowed per the terms and conditions and you will be reported to the authorities
EXACTLY, prepare to self deport immediately, push <proceed> to execute
„The joint service offering will provide the bundled compute, model, and licenses, while ensuring customer-specific design data is protected.“
I am not sure if Nvidia want to send their chip designs to OpenAI.
its like a fox starting a chicken coop business
Having written a lot of Tcl glue for PrimeTime and ICC, the hard part was never writing the constraints, it was knowing which timing violation to actually believe.
Give us more open source EDA tools, not more hyped up EDA vendors.
The goal - obviously - is the exact opposite.
Toolcalls will end up disappearing to the other side and then you can download the end result - at a price - or arrange for manufacturing, but you'll have no idea about what is in the nice & shiny black box.
A question to those active in chip design industry: Are formal methods and formally proving a design more prevalent and normal in this industry compared to general software development?
Like for a Arm microcontroller design, do engineers thoroughly test and formally prove the correct functionality of every component? If that's the case, why silicon errata is a thing?
It’s called design verification, formal proofs happen mostly at the EDA tool level and largely already automated. Design verification focus on functional correctness of the chip for its intended use case
There are tools for formal verification of design input, and they are being used, but not for everything.
Why there are still errata for silicon
1. Writing a formal specification of your intended behavior is hard and the best verification tool doesn't help when your assertions don't encode the required or intended behavior. So even with 100% formal coverage, you would still get erratas. And some people don't write any formal verification, instead working with a simulation based approach (either hand-written test cases or random stimulus simulation) 2. Computation complexity of formal verification is exponential. At some point you simply can't formally prove the behavior of a design, because it just won't run on your server. 3. There's different levels of formal verification, not all of them are in the spec -> behavior path. For example, you could classify automated checks like logic equivalence between the synthesis netlist and RTL code as a formal verification. But that checks if the optimizer in the synthesis tool was correct, not that you wrote the correct RTL.
Compared to software formal methods have greater adoption. But there are a lot of things that fall under the “formal” umbrella.
The most common type that is used would probably be logical equivalence checking. Proving RTL and a netlist are equivalent is useful for catching synthesis bugs.
Or proving two netlists are equivalent after inserting test functions directly into a netlist, or some other netlist edit.
Property checking is what I use the most. You can check these during simulation which I wouldn’t call “formal” but you can also prove them using tools that use SAT solvers and whatnot to prove things mathematically.
As always, the tricky part of verification is writing the correct test or model. With formal we can use SystemVerilog assertions to write properties and sequences, but the difficulty in getting them right goes from trivial -> inscrutable very quickly.
It’s extreme easy to write assertions that pass and never realize your assertion was not doing what you thought and you weren’t proving what you meant to.
I haven’t used some of the more advanced tools so maybe they have ways to make this easier. But because of this I tend to just write assertions that are pretty easy to understand at a glance, and therefore closer to the trivial side of things.
If a peer has to solve a sudoku puzzle in their head to understand your work, then it’s unlikely the peer review will be worth anything. So I do what I can to make my work understandable at a glance (from a competent peer in the industry).
Of course making something simple can be quite challenging and often takes more time than leaving something complex and opaque.
I’ve never been involved in the foundry side of the work, and for ASICs, that is often half of the schedule.
Apparently SNPS share price gone up a little bit because of this. However, the rise didn't compensate their loss over the years. I keep wondering why EDA companies didn't get the hype like AI labs and Chip design companies.
I remember the stock taking a beating after Kimi K3 created all that buzz about the open model designing chips that could run itself (even though the chip in question seemed small in today's standard of massive AI chips). It was only a matter of time before Synopsys released an offering like this. I can almost see the meeting where the C suite demanded working with an external partner over anything in-house they could build.
Why the overall market cap is smaller than both Synopsys and Ansys combined before the merger still beats me tho.
Something like JLCPCB but for chips would be revolutionary.
Can't wait for vibe coded SoCs.
Would be really nice honestly. But I don't think it will be coming anytime soon, it's just too expensive to build a chip. The one-time costs for masks are just much more expensive as for PCBs, so wafer shuttle services are still really expensive when pooled PCBs are really cheap. And any machines that would be cheaper for prototyping (direct laser writing or direct e-beam writing) don't scale to mass production.
You can already make (tiny) chips for a somewhat affordable cost with tiny tapeout. But that's still not nearly as cheap as PCB prototypes and with much longer wait times.
Prompt injection in hardware! What could possibly go wrong?
Astra is amazing with open PDKs. ;)